Class D amplifiers (CDAs) are becoming ubiquitous due to their significantly higher power-efficiency characteristics over their linear counterparts. For example, the commercial market size for CDAs in 2012 was estimated to be worth about two billion devices that incorporate CDAs (implemented in discrete/SoCs form factors), such as in smartphones, tablets, TVs, audio amplifiers, radios and the like. The attribute of CDAs having high power-efficiency is largely due to digital-like switching operation of associated output stages, in which power transistors arranged therein function as switches with low on-resistance. The high power-efficiency attribute is highly desirable as it translates to longer battery lifespan and elimination of usage of (or at least requires smaller) heat sinks.
Referring to FIG. 1, a CDA 100 typically comprises analog signal-processing circuits 102 (which may include an integrator 104, a modulator 106, a carrier generator 108, and a feedback network 110), and an output stage 112 (which may drive a load such as a loudspeaker 114). The integrator 104 provides a high loop-gain to suppress unwanted noise and distortions. The modulator 106 modulates output of the integrator 104 to a digital-like pulse signal. The output stage 112 buffers the pulse signal and drives the loudspeaker 114 by switching on/off the associated output transistors. The feedback network 110 feeds the output (from the output stage 112) back to the integrator 104 to form a closed-loop, thereby improving the linearity characteristics of the CDA 100 by means of negative feedback. The modulation techniques that may be adopted by the CDA 100 include Pulse Width Modulation (PWM), Bang-Bang control modulation, Sigma-Delta modulation, and Self-Oscillation modulation. Amongst those techniques, PWM is most commonly used because of its simple hardware requirement and high linearity characteristics. The Bang-Bang control modulation, on the other hand, is the most power-efficient for micro-power low voltage applications (e.g. hearing aids) because of its simplest hardware requirement. Although Sigma-Delta modulation and Self-Oscillation modulation potentially feature higher linearity than PWM and Bang-Bang control modulation, this advantage is however achieved at a cost of increased hardware complexity, and hence leading to lower power-efficiency.
Irrespective of the modulation techniques utilized, a congruity in the design of CDAs is the ground-bounce (noise) generated due to the switching operation of the output stage(s) of the CDAs. The ground-bounce is defined as large voltage spikes (on the otherwise clean supply rails), which may result in significant reliability degradation and compromise the linearity performance of CDAs. FIGS. 2a and 2b respectively depict an ideal and a practical switching waveform 200, 250 of an output stage of a CDA. Specifically in FIG. 2b, the ground-bounce, occurring immediately after rise and fall of the practical switching waveform 250, is clearly apparent.
So due to ground-bounce, false switching in the output stage may occur, hence degrading the performance (including reliability and/or linearity). To illustrate the issue of false switching in the Class D output stage due to ground-bounce, schematics of a PWM CDA 300 is first depicted in FIG. 3. The different stages of the PWM CDA 300 are labeled with the same reference numerals as per FIG. 1 simply for ease of explanation and referencing. For good order, it is to be appreciated that the analysis below is also applicable to Class D amplifiers which use other modulation techniques, besides PWM. With reference to FIG. 3, false switching arises because ‘disturbances’ (due to ground-bounce) at the integrator outputs (i.e. see circuit points in FIG. 3 labeled as Vint-p and Vint-n) and at the carrier output (i.e. see circuit point labeled as VC) are different.
To illustrate the mechanisms of erroneous PWM pulses, consider a practical case in FIGS. 4a and 4b which respectively depicts critical ground-bounce coupling paths (i.e. shown as dashed lines in each figure) from various ground-bounce ‘sources’ (i.e. see circuit points in FIGS. 4a and 4b labeled as Vout-p, AVGND and AVDD) to an output of the integrator 104 (i.e. Vint-p) and an output of the carrier generator 108 (i.e. VC). For illustration simplicity, only the upper differential branch of an op-amp (i.e. Op) is depicted in FIG. 4a. It is also to be appreciated that circuit points in FIG. 4a labeled as Mn-p and Mp-p are the output stage transistors of the said op-amp, Op.
There are four coupling paths in the integrator 104 (as per FIG. 4a) and three coupling paths in the carrier generator 108 (as per FIG. 4b). The noise seen at Vint-p is different from the noise at VC. Specifically, it may be seen that the noise at Vint-p is due to ground-bounce on PVDD and PVGND (i.e. Vout-p is connected to PVDD and PVGND through output power transistors; see FIG. 3), and on AVGND and AVGND, and is coupled through Rfb1, Cint1, Cint3, Rz1 and Mp-p and Mn-p. On the other hand, from FIG. 4b, the noise at VC is mainly due to ground-bounce on AVDD and AVGND, and is coupled through two current mirrors (i.e. each being a current source, I) and a capacitor, CC. This difference between the noise at Vint-p and at VC is interesting and arguably somewhat counter-intuitive, because ground-bounce is typically assumed to be common noise. Conversely, because of the said difference and depending on a degree of difference (in magnitude and phase), false switching may inadvertently occur. For instance, a scenario of false switching in a CDA is depicted in FIG. 5, where the ground-bounce markedly disturbs VC while the disturbance to Vint-p is comparatively lesser, and it is this difference that consequentially gives rise to false switching.
To mitigate false switching, a conventional solution proposes using a comparator with a wide hysteresis (having a difference between upper and lower thresholds larger than the noise) and a long(er) response time to de-sensitize the CDA to the noise across its inputs. However, in PWM CDAs, a comparator generally tends to be used as the PWM modulator and typically features small-to-moderate hysteresis (i.e. on the order of a few mVs) and with relatively short response-time (i.e. of about a few nanoseconds) because a large hysteresis and/or long response time reduces the output dynamic range of the CDA and increases the overall delay. Furthermore, the ground-bounce spikes generated may be as high as a few hundred mVs and hence, a hysteresis of the said range is unrealistic practically.
Hence, the comparator is impervious to the ground-bounce only if the magnitude of the noise is small (i.e. lesser than the hysteresis of the comparator) and transiently fast-changing (i.e. of a high-frequency). It is well recognized that circuits with large switching currents, including CDAs (which includes audio CDAs and high-speed Class D supply modulator for power RF power amplifiers), switching mode power supply (DC-DC Converters), and other circuits with switching signals (with large current flow), tend to generate substantial ground-bounce, which consequently leads to significant performance degradation (such as reliability and/or linearity (e.g. Total Harmonic Distortion (THD)). Conventional design methodologies and practices to mitigate the ground-bounce noise are largely still empirical in nature, and the mechanisms for a CDA thereto are also largely un-investigated.
Another issue CDAs commonly face is their high susceptibility to power supply noise, which is quantified and qualified by Power Supply Rejection Ratio (PSRR) and Power-Supply Induced Intermodulation Distortion (PS-IMD). By means of negative feedback, the PSRR and PS-IMD may be improved by increasing the loop-gain of the CDA, which is a well-established technique. Conventional methods to increase the loop-gain often include applying multiple feedbacks, but typically limited to two feedback loops. Due to stability issues, triple (or more) feedback loops are difficult to realize or that their loop-gain may need to be reduced, in some cases, to even a lower level obtainable from a double-feed back.
To further explain, FIG. 6 depicts schematics of a conventional double-feedback PWM CDA 600, in which a loop filter thereof comprises two second order integrators. It is to be appreciated that compared to single-feedback PWM CDAs or double feedback PWM CDAs with first order integrators, the loop gain of the double-feedback PWM CDA 600 with second order integrators is significantly higher. In the loop filter of the double-feedback PWM CDA 600, there are configured a total of four poles and two zeros and for stability sake, positioning of the poles and zeros need to be carefully designed and the loop gain is also reduced significantly. Moreover, using multiple (i.e. triple or more) feedback loops result in instability or that the loop gain is only comparable (to a double feedback loop), despite using more feedback loops.
One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.